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ASIC Design

ASIC Design

ASIC Design Services to your specific requirements

easics offers design services for both digital and mixed-signal chips: system-on-chip, ASIC, ASSP and structured ASIC.

Being an independent design services company, easics can provide you with unbiased technology and system architecture advice that perfectly matches your project requirements, budget and schedule.

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First Time Right & Reusable Methodology

easics works with leading semiconductor wafer manufacturers such as TSMC, GLOBALFOUNDRIES, UMC, SMIC, ST, NXP, TowerJazz, LFoundry, ON Semi, X-FAB, ams and NEC, and can thus leverage this experience for your project.

We support a wide range of technology nodes: 0.35μm, 0.25μm, 0.18μm, 0.13μm, 90nm, 65/55nm, 40nm, 28nm, 16nm.

easics has developed a robust and reuse-friendly design methodology to build First Time Right silicon. It uses a coding style that leverages the benefits of a synthesis-based implementation flow to code at the highest possible abstraction level, thus protecting your investment in a readable and maintainable code database.

This methodology is proven by a myriad of successful First Time Right projects for customers such as NXP Semiconductors, Cochlear, Keysight, CMOSIS, Sony Depthsensing Solutions, ESA and many others.

Extra care is taken in design areas where technology dependent features are used (such as embedded memory blocks and analog macros). These areas are carefully isolated in the design database, in such a way that transitioning to a different technology can be realized with minimum effort. easics’ design style and in-house tools also allow to realize FPGA prototypes of sub-systems of your design, if you so desire.

ASIC Project Tasks

Depending on your requirements easics’ system architects and design engineers can help you with the following project tasks:

Feasibility study.
Functional requirements assessment.
System architecture definition.
Hardware-software trade-offs.
Third-party IP selection and integration.
Module level hardware design and verification.
Processor integration and embedded software design.
Top level simulation at RTL and gate level.
Hardware-software co-verification.
Synthesis from RTL level to gate level.
Formal verification.
FPGA prototyping of top-level or sub-level.
Design for test: boundary scan, internal scan.
Physical design and verification.
Static timing analysis (STA).
Power consumption analysis.
Sign-off with technology partner: foundry, packaging, test.
Measurements of prototype ICs in the lab.

easics’ IP Blocks for ASIC Designs

These IP blocks can be licensed for use in your design project:

nearbAI: AI close to the sensors
easics uses its expertise in system-on-chip design to develop small, low-power and affordable AI engines that run locally, close to your sensors.
Fully hardware TCP Offload Engine (TOE)
easics' TCP Offload Engine (TOE) can be used to offload the TCP/IP stack from the CPU and handle it in FPGA or ASIC hardware. This core is an all-hardware configurable IP block. It acts as a TCP server for sending and receiving of TCP/IP data. Because everything is handled in hardware very high throughput and low latency are possible.
S8 processor: tiny, customizable microcontroller core
The S8 is a tiny 8-bit processor, originally designed to control and manage dominantly analog ASICs.
DDRx memory controllers
We have very efficient DDRx SDRAM controllers. They excel in high throughput, low latency and versatility. Typical use case: in an FPGA, when the vendor-provided controller cannot be used.

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