ASIC and silicon IP design for a bluetooth chip

ASIC and silicon IP design for a bluetooth chip


Looking for an experienced partner in VHDL, Verilog, SystemVerilog and UVM to design the packet processor for a Bluetooth ASIC.

The customer is a semiconductor company who designs and manufactures ultra-low power chips for consumer applications.


Our solution

RTL development and verification
easics developed the RTL of the packet processor first time right.
UVM testbench development and integration
We integrated our testbench in the top level UVM testbench of the customer.
3rd party IP verification
Verified the 3rd party IP in the top level testbench.


easics created and verified a first time right bluetooth packet processor. The customer was very happy that all created IP was verified and tested in the top level of the full mixed-signal radio ASIC.

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