Work Packaged Projects

Work Packaged Projects

Work packaged Projects for ASIC and FPGA

easics your experienced partner in ASIC and FPGA design is offering his services as a work package project. These projects are delivered under a fixed scope and within an upfront agreed schedule and budget. We develop a digital macro for your ASIC or SoC projects as RTL, netlist or GDSII. We develop FPGA bitmaps and firmware for intel, Xilinx and microsemi.

ASIC digital macro

If your company is looking for ASIC design services, easics can offer you a solution in the form of a work package project. We are an experienced partner that can take the responsibility of the digital part of the chip design. Always talking into account the feasibility, size, power consumption and price of the design. This includes the following tasks:

Full RTL-to-GDS flow
Architecture (Mixed signal IC)
RTL implementation
Integration of processors and IP cores
RTL verification or validation
RTL optimisation and timing closure.
Register map
responsible of RTL synthesis and layout
Design for test (DFT)
FPGA conversion to custom ASIC
VHDL and Verilog
SystemVerilog, UVM or System C
ASIC design flow

FPGA development

If your company is looking for FPGA development, easics can offer you a solution in the form of a work package project. We are an experienced partner that can take the responsibility of the FPGA development of the design. This includes the following tasks:

Jump start your project and use best practices
VHDL & verilog RTL development
Xilinx Vivado or intel quartus environment
RTL verification with Systemverilog or SystemC
Embedded software or APIs for SoC
FPGA development