FPGA Design Copy

FPGA Design Copy

FPGA Design for reliable embedded systems

easics offers design services for FPGA-based embedded systems.

Being an independent design services company, easics can provide you with unbiased technology and system architecture advice that perfectly matches your project requirements, budget and schedule.

Our FPGA design services include:

FPGA hardware design: VHDL, SystemC, (System)Verilog / UVM, MyHDL
DSP, algorithm & model design: Matlab, SystemC, C++, C, Python, Ruby, …
embedded software design: C
FPGA development for early prototyping and emulation
prototype measurements
long-term support
work package projects

FPGA Design for devices of all vendors

easics works with FPGA devices of all vendors (Intel Xilinx Microsemi , …), including the use of the IP provided by those vendors. easics has experience with embedded software design for ARM , Microblaze and Nios, and using embedded Linux.

easics has developed a robust and reuse-friendly design methodology to build reliable embedded systems. It uses a coding style that leverages the benefits of a synthesis-based implementation flow to code at the highest possible abstraction level, thus protecting your investment in a readable and maintainable code database.

Moreover, this methodology enables the roll-out of a product roadmap, using scalable IP. This methodology has been proven in a number of FPGA designs, for multiple clients such as TOMRA Sorting .

FPGA Design Project Tasks

Depending on your requirements easics’ system architects and design engineers can help you with the following project tasks:

Feasibility study
Functional requirements assessment.
System architecture definition.
Hardware-software trade-offs.
Third-party IP selection and integration.
Module level hardware design and verification.
Embedded software design
Synthesis from RTL level to gate level.
Top level simulation at RTL and netlist.
Hardware-software co-verification.
Place & Route.
Static timing analysis (STA).
Power consumption analysis.
Measurements of prototype PCBs (with FPGA) in the lab.

easics’ IP Blocks for FPGA Designs

easics has developed an FPGA – IP library. It includes:

These IP blocks can be licensed for use in your design project:

Fully hardware TCP Offload Engine (TOE)
easics' TCP Offload Engine (TOE) can be used to offload the TCP/IP stack from the CPU and handle it in FPGA or ASIC hardware. This core is an all-hardware configurable IP block. It acts as a TCP server for sending and receiving of TCP/IP data. Because everything is handled in hardware very high throughput and low latency are possible.
DDRx memory controllers
We have very efficient DDRx SDRAM controllers. They excel in high throughput, low latency and versatility. Typical use case: in an FPGA, when the vendor-provided controller cannot be used.

Contact us for more information

We are happy to help you out.