DVCON Europe 2019


DVCON Europe 2019

As is almost tradition by now, we headed to Munich at the end of October for DVCon. Just as prior years, the place to be was the Holiday Inn, conveniently located next to an S-Bahn station with a direct connection to Munich’s airport.

Tuesday started off great with a very interesting keynote by NXP’s CTO Lars Reger. He talked about the necessity of moving away from the cloud and onto the edge, and of the need to do this safely and securely. This was a great overview of challenges to come and especially nice because it matches well with the goals of our deep learning IP.

The rest of the day, Tim and I split up so that we could attend as many tutorial sessions as possible. For example, a Synopsys-sponsored one on ISO26262-compliant verification really drove home the complexity of such an undertaking. A presentation on a library offering SystemVerilog-like functional coverage for SystemC was also really interesting, since we use SystemC a lot such functionality is a welcome addition to our tool-stack.

The many coffee- and food-breaks were very well organized by the hotel. We got a chance to sample some of the great cuisine Germany has to offer. Of course, we had to end our day with a refreshing Weissbier and some Bretzen (pretzels).

Wednesday was reserved for shorter presentations by non-sponsoring companies. Many of these touched upon various difficulties which we at one point or another encountered ourselves during verification. It was interesting to see how other companies tackle those issues.

Mikhail Moisseev’s talk on Intel’s in-house SystemC-to-Verilog tool was very fascinating. It reminded us of an in-house easics tool aimed at language-to-language conversion. We very much liked the fact that we seem to go for high-level design methodologies the same way big-name players such as Intel are.

This marked the official end of DVCon, but we chose to stay for the SystemC Evolution Day on Thursday. A bunch of interesting presentations coupled with a very engaging audience as well, made for a very instructive day.

The highlight for us was prof. Doemer’s presentation on parallelizing SystemC. Although it requires breaking some parts of the SystemC standard, his team’s combination of a custom instrumenting compiler and SystemC runtime showcased a simulation speed-up of up to 200x. Over lunch we had a great discussion on the intricacies related to this parallelization effort. Definitely something we will keep an eye on!

Unfortunately, we had to skip the last few presentations of the afternoon, since we would otherwise miss our return plane to Brussels. Unlike last year, we managed to reach the airport without any major hiccups. A stress-free end to a very interesting three days!

Anthony (Senior Design Engineer) & Tim (Project Leader)

More information: easics @ DVCON Europe