S8 processor

S8 bit processor

The S8 is a tiny processor, originally designed to control and manage dominantly analog ASICs.
The main goals of the S8 design are:

  • simplicity to use and to integrate
  • customizability
  • small footprint
  • technology independence

As it is intended to be used for housekeeping, performance is not a priority.
Therefore a very simple architecture has been chosen: the S8 has only a 2 stage pipeline (fetchexecute), no cache, no branch prediction, no MMU.
The S8 has 3 external busses:

  • the program memory bus: a 16-bit address, 16-bit data bus. Most instructions of the S8 are 16 bit instructions, fitting in one memory word. Only a few instructions, containing large immediate values, use 32 bit and occupy 2 words. A memory (RAM and/or ROM) of up to 64k words can be connected to the program memory bus.
  • the data memory bus: a 16-bit address, 8-bit data bus, to connect the processors data memory. Up to 64k byte of memory can be connected.
  • the I/O bus: a 16-bit address, 8-bit data bus, intended to be connected to peripheral interfaces.

The S8 has a proprietary parallel debug interface. As part of the integration of the S8, a bridge needs to be designed to make the debug functionality available for the end user.

The debug interface provides following functionality:

  • control the processors run/halt state
  • read and modify the content of all registers
  • read and update the program memory (to set software breakpoints)
  • read and modify the data memory