Easics has modeled, implemented and verified proprietary digital pixel processing algorithms for CMOSIS’ novel intelligent CMOS image sensor chip for the “Leica M” camera. Easics’ model-based approach resulted in first time right silicon.

Easics created a high-level model of the proprietary digital noise cancellation and correlated double sampling algorithms for the CMOSIS “Leica MAX 24MP CMOS Sensor” chip. This model gradually precedes over the textual specification document, while iteratively refining it. It becomes a bit-true executable specification. Important executable use cases (main operational modes as well as corner case behavior) emerged naturally from this iterative refinement. They form the basis of the regression-based verification suite, and enable test-driven development. Easics used the model as reference for all verification. CMOSIS signed off on it, turning it into a formal decoupling point between the specification document and the detailed implementation.

Frequent specification changes are part of the game in leading-edge mixedsignal ASIC developments. In this development, they merely lead to iterations on the high-level model, rather than on detailed implementations (which would potentially cause major rework and schedule slips). The model-based approach is hence a key design productivity enabler, as the model is designed at the “right” level of abstraction for its purpose: right before converting the “what” into the “how”. It drastically improves the time-to-market and keeps the budget under control.

Easics further used the model as reference for the detailed implementation. It enabled continuous integration, as the model served as an initial version of the implementation. Implementation decisions such as mathematical operator implementation, pipelining and clockgating took into account performance, area and power constraints.

A model is unambiguous and “richer” than a natural language specification. It is elegant thanks to its high abstraction level and the use of available libraries.

This model-based approach proved to be highly effective for CMOSIS’ high dynamic range, 24 megapixel full-frame35mm format CMOS image sensor chip development for Leica. Proprietary innovations in both digital and analog domains resulted in low temporal and spatial noise and non-uniformities. First-time right silicon success was achieved on time and in a tight schedule. Leica Camera AG launched the new “Leica M” camera, containing this chip, at Photokina 2012 in Cologne, Germany.

This approach is part of easics’ mixed-signal ASIC design toolbox. It is ideally suited for datapaths and signal processing, and is complemented with techniques such as SystemC and Verilog-AMS modeling and in-the-loop simulation. Easics creates the model in the high-level language that the customer prefers, such as C++ / SystemC, Matlab, Python, or Ruby. This fits nicely in easics’ vision of maximally using software techniques and high levels of abstraction for chip design and verification. Easics uses similar high-level modeling techniques for advanced FPGA development.

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