Design Conceptualization

Design Conceptualization

Design Conceptualization to your specific requirements

You are a company that is ready to use an ASIC or an FPGA in your product. You are looking for a partner that can jointly define the concept and the specification of the ASIC and FPGA. easics’ system architects can guide you through the requirements engineering phase and help you with the launch of your project.

Start your project with easics

Depending on your requirements easics’ system architects and design engineers can help you with the following project tasks:

concept flow website
Requirements engineering
Every successful project starts with a profound requirements analysis. In this phase we cover all needs and functions for the project in order to have a clear benchmark for future steps in the process. After the requirements engineering stage, we can dig deeper into the feasibility and architecture.
Feasibility study and architecture
In this stage we evaluate the feasibility of the current project idea in terms of budget, timing and technical possibilities. We also define the system architecture. The feasibility study phase is a crucial part of the process since it gives all parties involved a clear foundation for all the next steps.
Decision aids and project launching
After the previous phases we know what to do and how we can do it. Now it all comes down to making the right decisions. We give the decision makers and other stakeholders a clear view of the challenge that lies ahead. We can point out the most essential parts that need to get formal approval before the project launch.

Licensed IP Blocks

These IP blocks can be licensed for use in your design project:

nearbAI: AI close to the sensors
easics uses its expertise in system-on-chip design to develop small, low-power and affordable AI engines that run locally, close to your sensors. nearbAI can be mapped on ASIC or FPGA.
Fully hardware TCP Offload Engine (TOE)
easics' TCP Offload Engine (TOE) can be used to offload the TCP/IP stack from the CPU and handle it in FPGA or ASIC hardware. This core is an all-hardware configurable IP block. It acts as a TCP server for sending and receiving of TCP/IP data. Because everything is handled in hardware very high throughput and low latency are possible.
S8 processor: tiny, customizable microcontroller core
The S8 is a tiny 8-bit processor, originally designed to control and manage dominantly analog ASICs.
DDRx memory controllers
We have very efficient DDRx SDRAM controllers. They excel in high throughput, low latency and versatility. Typical use case: in an FPGA, when the vendor-provided controller cannot be used.

Experienced partner

easics offers thorough consulting and analysis services for your specific project. Based on our 30 years of experience, we noticed that it is always beneficial when we are already involved in the early stages of projects. In most cases, the consulting and study phases lead to further cooperation in the development process with work-package projects, consultancy or solutions such as IP cores.