nearbAI on FPGA
AI IP core – Deep Learning Accelerator
easics has created a parameterizable AI IP core that can be deployed on intel and Xilinx FPGA’s examples are intel Arria10, Cyclone10 and Xilinx Zynq, Zynq ultrscale+. The deep learning model and the constraints of your application like performance, latency, power consumption and cost defines the right parameters of the nearbAI core as inference engine. The nearbAI software development suite will convert the model and the weights into an FPGA build file that is ready to deploy on the chosen FPGA hardware.
Why choose nearbAI as AI accelerator?
nearbAI software development suite
easics’ deep learning framework can support your neural networks based on existing frameworks like Tensorflow, Caffé, python, ONNX, C/C++, …The input for the framework is the network description and the weights of the trained deep learning model. The nearbAI compiler is converting the network description in a runtime schedule as microcode and the weights of the trained model in fixed point by floating point quantization. The estimator GUI provides the right hardware configuration and performance for the chosen FPGA or enables the choice of the right FPGA. When your nearbAI core is configured and the FPGA is chosen the FPGA configuration file is generated.
The diagram summarizes the automated hardware implementation flow. The hardware parmeters describes the number of multipliers, buffer sizes, interface widths and clock frequencies. The ONNX model file contains the CNN network topology and the parameters (weights, bias, …). The hardware generation results in an FPGA configuration file (bitfile) based on primitive CNN operations and a scaled amount of available FPGA resources. The microcode or sequence generation is a compiled program of low-level commands to run the AI acceleration.
Deep learning on FPGA
The FPGA is divided into 2 parts, the hardwired ARM subsystem and the FPGA configurable logic The design is connected to a SDRAM, which is accessible by the ARM processor as well as by the programmable logic of the FPGA via a switch matrix. It is used by the ARM processor as working memory for the Linux operating system, and by the easics AI core for weights, activations, IO data and the sequence or microcode.
The easics AI core has 3 interfaces: It is a master on the data memory bus. It is a master on the instruction memory bus. It is a slave on the ARM processors IO bus.
Deep learning on FPGA – download PDF documentation
Want to know more about nearbAI on FPGA?
Request a demo or evaluation kit!
Intel Arria 10 Evaluation System
- mapping of your model(s) on the hardware
- quantization of the weights and tensors
- nearbAI evaluation core parameterized for your performance
- embedded software (running on the processor system)
- ARM linux driver
- ARM linux application
- Ethernet, USB and HDMI
- SFP+ for 10GigE
- Supports Quartus design flow
- Runs on ReflexCES achilles instant development kit or PCIe Carrier Board Arria 10 SoC SoM Development Kit
- Python or C++ API is provided to interface with the FPGA board
- The API will be able to load images and weights on the FPGA and return the inference results
Xilinx Zynq UltraScale+ MPSoC Evaluation System
- mapping of your model(s) on the hardware
- quantization of the weights and tensors
- nearbAI evaluation IP core parameterized for your performance
- embedded software (running on the processor system)
- ARM linux driver
- ARM linux application
- Ethernet, USB, HDMI and MIPI
- SFP+ for 10GigE
- Supports vivado design flow
- Runs on Xilinx ZCU104 instant development kit
- Python or C++ API is provided to interface with the FPGA board
- The API will be able to load images and weights on the FPGA and return the inference results
Which customers benefit from deep learning on FPGA?
The nearbAI accelerator offers benefits to machine builders, semiconductor companies and even manufacturing companies.
