Easics has developed a number of IP blocks. You can license them for use in your FPGA or ASIC design. Additionally, Easics design engineers can help you with the IP integration and verification in your design project.
For more information on licensing terms and pricing, please contact us. See Contact Us.
Our TCP/IP core is a hardware implementation of the TCP/IP protocol. It does not require any software and can easily be integrated in your design.
It exists in 2 versions:
- 1 Gbit/s
- 10 Gbit/s
The design is highly efficient and realizes near maximum data throughput. Additionally, the TCP/IP core has an extremely low latency.
The cores have been successfully integrated in projects targeted at several different Xilinx and Altera devices.
DDRx SDRAM controller
We have very efficient DDRx SDRAM controllers. They excel in high throughput, low latency and versatility.
Typical use case: in an FPGA, when the vendor-provided controller cannot be used.
This is a tiny, customizable microcontroller core, available in 8-bit data widths, hence the name S8.
The core is usable as is, or we can customize it to your precise needs. E.g. we can add a multiplier, tailor the memory interfaces to your embedded memory of choice, tailor the debug-port,… This guarantees the smallest chip area. Assembler and debugger tools are provided. The learning curve is very short.
Typical use case: in a mixed-signal ASIC, to calibrate, configure and control the analog macro(s).