Designing digital circuits is already supported by a lot of excellent EDA tools, such as logic synthesis or test insertion tools. However, some design aspects can be automated but don't quite fit into the EDA vendor model. For example, the interconnection of a number of modules in a higher level module or getting your simulation up-to-date with the latest code updates from your design repository. In such cases, Easics has developed its own tools to speed up the design process.

Below you find a list of some of the tools:

• ariadne: automatic creation of hierachical modules as an interconnection of lower level modules.
• VCI: hardware-software interface design tool.
• cma, vma, sma: Makefile generation for simulation (both hardware and software side) and synthesis.
• crctool: a tool to generate VHDL or verilog code for CRC functions. This function is available free of charge on our website.

Easics uses these tools on its own design projects, but is willing to discuss licensing options with you. Contact us for more information.