Easics offers design services for both digital and mixed-signal chips: system-on-chip, ASIC, ASSP and structured ASIC. Being an independent design services company, Easics can provide you with unbiased technology and system architecture advice that perfectly matches your project requirements. Easics works with leading semiconductor wafer manufacturers (TSMC, GLOBALFOUNDRIES, UMC, SMIC, TowerJazz, LFoundry, ON Semi, NXP, etc.) and can thus leverage this experience for your project.
Easics has also developed its own robust and reuse-friendly design methodology to build first-time right silicon. It uses a coding style that leverages the benefits of a synthesis-based implementation flow to code at the highest possible abstraction level, thus protecting your investment in a readable and maintainable code database. This methodology is proven by a myriad of successful first-time right projects for customers such as NXP, Cochlear, Agilent / Keysight, CMOSIS, ESA and others...
Extra care is taken in design areas where technology dependent features are used (such as RAMs). These areas are carefully isolated in the design database, in such a way that transitioning to a different technology can be realized with minimum effort. Easics' design style and in-house tools also allow to realize FPGA prototypes of sub-systems of your design, if you so desire.
Depending on your requirements Easics' system architects and design engineers can help you with the following project tasks:
- Feasibility study.
- System architecture definition.
- Hardware-software trade-offs.
- Functional requirements assessment.
- Module level design, verification and implementation.
- Top level simulation at RTL and gate level.
- Third-party IP selection and integration.
- Hardware-software co-verification.
- Synthesis from RTL level to gate level.
- FPGA prototyping of top-level or sub-level.
- Design for test: boundary scan, internal scan.
- Static timing analysis.
- Signoff with selected technology partner.
Easics has also developed its own IP library. This library includes:
- Hardware TCP/IP core.
- Tiny/customizable microcontroller cores.
- DDRx memory controllers.
These IP blocks can be licensed for use in your design project. Please contact us for more information.