Ramses Valvekens is the Chief Executive Officer (CEO) of Easics, since the management buy-out in December 2004.
Besides his role as CEO, Ramses remains active as a systems architect, focusing on technology selection, project risk reduction and cost-effective mixed-signal ASIC and FPGA design trade-offs. He is a regular speaker at industry conferences and gives lectures in semiconductor system design.
He holds a Master degree (1997) in Electronics Engineering from the Katholieke Universiteit Leuven and a Master degree (1994) in industrial engineering / electronics from Groep T in Leuven, Belgium.
He performed research in signal processing at the Lawrence Livermore National Laboratories (California, USA) and at the Institut National Polytechnique de Grenoble (France).
In 1994, he won the Barco/VIK prize for the design of an FPGA-based reconfigurable processor for industrial image processing in cooperation with imec.
He has been working at Easics since 1997. During the TranSwitch years (2000 till 2004), he was technical manager of a product family of mixed-signal telecom chips. He received the TranSwitch Employee Recognition Award in 2003 and is co-inventor of two telecommunication patents.
Steven Coenen is the Chief Technology Officer (CTO) of Easics, since the management buy-out in December 2004.
He holds a Master degree (1998) in Computer Engineering from the Katholieke Universiteit Leuven, Belgium.
He has been working at Easics since 1998 and has developed most of the Easics in-house EDA tools to support Easics’ design methodology.
He is an all-round hardware/software guru and a vivid GNU/Linux adept.
He is the inventor of a patent on the verification of telecom protocols.